Integrated circuits are often designed to incorporate scan test circuitry that facilitates testing for various internal fault conditions. Such scan test circuitry typically comprises scan chains comprising multiple scan cells. The scan cells may be implemented, by way of example, utilizing respective flip-flops. The scan cells of a given scan chain are configurable to form a serial shift register for applying test patterns at inputs to combinational logic of the integrated circuit. The scan cells of the given scan chain are also used to capture outputs from other combinational logic of the integrated circuit.
Scan testing of an integrated circuit may therefore be viewed as being performed in two repeating phases, namely, a scan shift phase in which the flip-flops of the scan chain are configured as a serial shift register for shifting in and shifting out of respective input and output scan data, and a scan capture phase in which the flip-flops of the scan chain capture scan data from combinational logic. These two repeating scan test phases are often collectively referred to as a scan test mode of operation of the integrated circuit.
Outside of the scan test mode and its scan shift and capture phases, the integrated circuit may be said to be in a functional mode of operation. Other definitions of the scan test and functional operating modes may also be used. For example, the capture phase associated with a given scan test may instead be considered part of a functional mode of operation, such that the modes include a scan shift mode having only the scan shift phase, and a functional mode that includes the capture phase.
In scan testing of an integrated circuit, signal transitions associated with various applied test patterns are “launched” via the scan cells. Such transitions may be launched using a variety of different techniques, including launch-on-shift and launch-on-capture techniques, which are also referred to herein as respective “launch modes.” In the launch-on-shift technique, a signal transition is launched from a scan input of a scan cell to an output of the scan cell, while in the launch-on-capture technique, a signal transition is launched from a functional input of the scan cell to an output of the scan cell. It should be noted that the scan cell may include separate scan and functional outputs, or a single common scan and functional output.
Integrated circuits commonly include multiple clock domains. In an integrated circuit of this type, different portions of the integrated circuit are provided with different clock signals via a clock distribution network. Different scan chains or other types of sets of scan cells, including multiple sets of scan cells of a given single scan chain, may each be associated with a different clock domain.
In conventional practice, the scan cells of the multiple clock domains are all typically configured to utilize the same transition launch technique at the same time. For example, all of the clock domains at a particular launch time may be configured to utilize either the launch-on-shift technique or the launch-on-capture technique. Thus, the multiple clock domains either all launch signal transitions using the scan inputs of the scan cells or all launch signal transitions using the functional inputs of the scan cells. Such an arrangement tends to place significant limitations on the flexibility of the scan testing operation. As a result, test duration may be unduly increased for a given level of fault coverage, or fault coverage may be unduly limited for a given test duration.